1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a non-volatile memory (NVM) device and a manufacturing method and an operating method thereof.
2. Description of Related Art
Electrically erasable programmable read only memory (EEPROM) is a type of non-volatile memory that allows multiple data reading, writing and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computer and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon, and the control gate is disposed directly above the floating gate. Further, the floating gate is isolated from the control gate with a dielectric layer, while the floating gate is isolated from the substrate with a tunnel oxide layer. With the control gate, the floating gate, the dielectric layer and the tunnel oxide layer, a stacked gate flash memory cell is provided.
FIG. 1 is a schematic cross-sectional view of a portion of a conventional stacked gate flash memory cell structure (refer to U.S. Pat. No. 6,214,668). As shown in FIG. 1, the conventional stacked gate flash memory cell structure includes a p-type substrate 100, a deep n-well region 102, a p-type pocket doped region 104, a stacked gate structure 106, a source region 108, a drain region 110, a spacer 112, an interlayer dielectric layer 114, a conductive plug 116 and a conductive line 118 (bit line). The stacked gate structure 106 is constituted with a tunnel oxide layer 120, a floating gate 122, a gate dielectric layer 124, a control gate 126 and a cap layer 128. The deep n-well region is disposed in the p-type substrate 100. The stacked gate structure 106 is positioned on the p-type substrate 100, while the source region 108 and the drain region 110 are configured in the p-type substrate beside two sides of the stacked gate structure 106. The spacer 112 is disposed on the sidewall of the stacked gate structure 106. The p-type doped region 104 is configured in the deep n-well 102 and is extended from the drain region 110 to the underneath of the stacked gate structure 106. The interlayer dielectric layer 114 is positioned on the p-type substrate 100. The conductive plug 116 penetrates through the interlayer dielectric layer 114 and the p-type substrate 100 to short the drain region 110 with the p-type packet doped region 104. The conductive line 118 is disposed on the interlayer dielectric layer 114 and is electrically connected with the conductive plug 116.
With the continuous miniaturization of semiconductor devices as the level of integration of integrated circuits increases, the dimension of memory cells must also reduces in order to increase the level of integration. According to the stacked gate flash memory cell in FIG. 1, reducing the dimension of a memory cell can be accomplished by reducing the gate length of the memory cell. However, when the gate length is being reduced, the channel length under the tunnel oxide layer is reduced correspondingly. Thus, an abnormal punch through between the source region and the drain region easily occurs, which greatly affect the electrical performance of the memory cell, Moreover, two neighboring memory cells may interfere with each other to slow down the operating speed of the device. Consequently the effect of the device is affected. Apart from the above-mentioned deficiencies, the reduction of the dimension of the flash memory is limited by the critical dimension of the photolithography process applied in the fabrication of the flash memory.